1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having noise tolerant input buffer.
2. Brief Description of the Related Art
Higher level of integration, higher speed of operation, and lower power consumption had been and still are design goals for semiconductor memory device designers. The increased operational speed in the devices requires increased switching, increased current surges, and thereby increased occurrences of noise. The higher speed memory devices therefore operate in a noiser environment. When not properly controlled, noise can cause false operations in data and address signaling and read/write operations, rendering the device unreliable or even useless.
FIG. 1 is a structure of a conventional address buffer in a semiconductor memory device. Referring to FIG. 1, the address buffer includes a NOR gate 1 receiving an external address signal XAi and a chip enable buffer signal /CE, a plurality of inverters 2-5 connected to the NOR gate 1 in series, first and second short pulse generators 7 and 8 connected to the inverter 5, and an inverter 6 connected to the inverter 5. The first short pulse generator 7 generates a first short pulse having logic xe2x80x98highxe2x80x99 SPGHi and the second short pulse generator 8 generates a second short pulse having logic xe2x80x98lowxe2x80x99 SPGLi. The address buffer is used to buffer the external address signal XAi, generate an address signal Ai in response to the chip enable buffer signal /CE, and transfer the output signal Ai to a memory cell array of the semiconductor device.
FIG. 2 is a structure of a conventional chip enable buffer for buffering an external chip enable buffer signal /XCE and generating a chip enable buffer signal /CE. The chip enable buffer includes a NOR gate 11 receiving an external chip enable signal /XCE, a plurality of inverters 11-15 connected to the NOR gate 11, a third short pulse generator 17 connected to the inverter 15 for generating a chip enable short pulse signal CESP, and an inverter 16 connected to the inverter 15. Customarily, if the external chip enable signal /XCE is logic xe2x80x98high,xe2x80x99 the semiconductor device is disabled or put in a standby mode and if the external chip enable signal /XCE is logic xe2x80x98low,xe2x80x99 the semiconductor device is enabled. When the semiconductor device is on standby, it consumes only a small amount of current. The chip enable short pulse signal CESP generated by the third short pulse generator 17 is a control signal for transferring the first short pulse having logic xe2x80x98highxe2x80x99 SPGHi and the second short pulse having logic xe2x80x98lowxe2x80x99 SPGLi into a sense amplifier control circuit when the external chip enable signal /XCE is shifted from logic xe2x80x98highxe2x80x99 to xe2x80x98lowxe2x80x99 or from logic xe2x80x98lowxe2x80x99 to xe2x80x98highxe2x80x99.
FIG. 3 is a block diagram of a conventional semiconductor memory device for reading data. The conventional memory device includes an address buffer 10, a chip enable buffer 20, a decoder 30, a summator 40, a memory cell array 50, a sense amplifier control circuit 60, a sense amplifier 70, and a data output buffer 80.
The function and internal circuits of the address buffer 10 and chip enable buffer 20 are described above with reference to FIGS. 1 and 2. The summator 40 is a circuit for generating another short pulse when any short pulse is generated at the address buffer 10 and chip enable buffer 20. The sense amplifier control circuit 60 is driven by the short pulse generated at the summator 40 and is for controlling the sense amplifier 70 at a desired time.
FIG. 4 is an operational timing diagram of the signals of the conventional semiconductor memory device shown in FIG. 3. If the external chip enable signal /XCE includes noise while the chip enable buffer 20 is enabled, the noise can be amplified by the chip enable buffer 20 and a false pulse can be generated. The false pulse can cause a read operation when no read was intended. In most memory devices, the read operation will clear the data stored in the cell.
As described above, a problem in a conventional semiconductor memory device is that the semiconductor memory device performs false operations if noise is present in the chip enable buffer. Thus, a need exists for a semiconductor device having a noise tolerant chip enable buffer.
A semiconductor memory device is provided, which includes: a chip enable buffer generating first and second control signals having opposite phases of logic, the first and second control signals enabling and disabling operations of the semiconductor memory device, respectively; and an address buffer comprising an input terminal, and a blocking terminal connected to the input terminal, the input terminal receiving an external address signal under control of the first control signal, and the blocking terminal generating an address signal in response to the second control signal.
According to an embodiment of the present invention, the address buffer further includes a shift detecting circuit connected to the blocking terminal for generating first and second short pulses by detecting shift of the address signal, wherein the pluses are used as signals for reading data of the semiconductor memory device. The address buffer further includes an inverter between the blocking terminal and the shift detecting circuit.
According to an embodiment of the present invention, the shift detecting circuit includes: a first short pulse generator generating the first short pulse when the shift of the address signal is changed from logic xe2x80x98lowxe2x80x99 in logic xe2x80x98highxe2x80x99 and a second short pulse generator generating the second short pulse when the shift of the address signal is changed from logic xe2x80x98highxe2x80x99 in logic xe2x80x98lowxe2x80x99. The input terminal includes a NOR gate receiving the external address signal and the input terminal generates a data-in signal in response to the first control signal. The input terminal further includes an inverter.
The input terminal includes a NAND gate receiving the external address signal and generating a data-in signal in response to the first control signal. The blocking terminal includes: a switch receiving the data-in signal and generating an output signal by opening or closing in response to the second control signal; and a latch for storing the output signal, preventing generation of a false pulse due to noise, and generating the address signal. The switch includes: first and second PMOS transistors; and first and second NMOS transistors, wherein the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, ant the second NMOS transistor are connected in series, the first PMOS transistor is connected to logic xe2x80x98highxe2x80x99 and the second NMOS transistor is connected to logic xe2x80x98lowxe2x80x99, the data-in signal is input to gates of the second PMOS transistor and the first NMOS transistor, the second control signal is connected to gates of the second NMOS transistor and the first PMOS transistor through an inverter, and the output signal of the switch is connected to a connecting node of the second PMOS transistor and the first NMOS transistor. The switch includes: interconnected PMOS and NMOS transistors; and an inverter, wherein the data-in signal is input to one side of the interconnected PMOS and NMOS transistors, and the second control signal is input to a gate of the NMOS transistor and a gate of the PMOS transistor through the inverter. The chip enable buffer includes: a input part receiving an external chip enable signal and generating the first control signal; and a plurality of inverters in series connected to the input part for amplifying the first control signal; an inverter for generating the second control signal, wherein the inverter connected to the plurality of inverters. The input part is a NOR gate.
A semiconductor memory device is also provided, which includes: a chip enable buffer generating first and second control signals having opposite phases of logic, the first and second control signal enabling or disabling operations of the semiconductor memory device; an address buffer receiving an external address signal controlled by the first control signal and, generating an address signal in response to the second control signal, and generating first and second short pulses by detecting shift of the address signal; a memory cell array including memory cell transistors having data, the memory cell array receiving the address signal; a sense amplifier control circuit for receiving the first and second short pulses; and a sense amplifier for reading the data in the memory cell array in response to the first and second short pulses.
According to an embodiment of the present invention, the chip enable buffer includes: a input part receiving an external chip enable signal and generating the first control signal; and a plurality of inverters in series connected to the input part for amplifying the first control signal; an inverter for generating the second control signal, wherein the inverter connected to the plurality of inverters. The address buffer includes an input terminal, and a blocking terminal connected to the input terminal, the input terminal receiving an external address signal controlled by the first control signal, the blocking terminal generating an address signal in response to the second control signal, and a shift detecting circuit connected to the blocking terminal for generating first and second short pulses by detecting shift of the address signal.
According to an embodiment of the present invention, the semiconductor memory device further includes an inverter between the blocking terminal and the shift detecting circuit. The shift detecting circuit includes: a first short pulse generator generating the first short pulse when the shift of the address signal is changed from logic xe2x80x98lowxe2x80x99 to logic xe2x80x98highxe2x80x99 and a second short pulse generator generating the second short pulse when the shift of the address signal is changed from logic xe2x80x98highxe2x80x99 to logic xe2x80x98lowxe2x80x99.
A method for generating an address signal in a semiconductor memory device is also provided, the method includes the steps of: generating first and second control signals; receiving an external address signal in response to the first control signal; and generating the address signal by filtering the external address signal in response to the second control signal.
According to an embodiment of the present invention, the first and second control signals are opposite phase each other. The method further includes the steps of; generating a first short pulse when shift of the address signal is changed from logic xe2x80x98lowxe2x80x99 to logic xe2x80x98highxe2x80x99 and generating a second short pulse when shift of the address signal is changed from logic xe2x80x98highxe2x80x99 to logic xe2x80x98lowxe2x80x99.